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#### 3.17.1 AArch64 Options

These options are defined for AArch64 implementations:

`-mabi=`name
  Generate code for the specified data model. Permissible values are ‘`ilp32`’ for SysV-like data model where int, long int and pointer are 32-bit, and ‘`lp64`’ for SysV-like data model where int is 32-bit, but long int and pointer are 64-bit.

  The default depends on the specific target configuration. Note that the LP64 and ILP32 ABIs are not link-compatible; you must compile your entire program with the same ABI, and link with a compatible set of libraries.

`-mbig-endian`
  Generate big-endian code. This is the default when GCC is configured for an ‘`aarch64_be-*-*`’ target.
`-mgeneral-regs-only`
  Generate code which uses only the general registers.
`-mlittle-endian`
  Generate little-endian code. This is the default when GCC is configured for an ‘`aarch64-*-*`’ but not an ‘`aarch64_be-*-*`’ target.
`-mcmodel=tiny`
  Generate code for the tiny code model. The program and its statically defined symbols must be within 1GB of each other. Pointers are 64 bits. Programs can be statically or dynamically linked. This model is not fully implemented and mostly treated as ‘`small`’.
`-mcmodel=small`
  Generate code for the small code model. The program and its statically defined symbols must be within 4GB of each other. Pointers are 64 bits. Programs can be statically or dynamically linked. This is the default code model.
`-mcmodel=large`
  Generate code for the large code model. This makes no assumptions about addresses and sizes of sections. Pointers are 64 bits. Programs can be statically linked only.
`-mstrict-align`
  Do not assume that unaligned memory references will be handled by the system.
`-momit-leaf-frame-pointer`
`-mno-omit-leaf-frame-pointer`
  Omit or keep the frame pointer in leaf functions. The former behaviour is the default.
`-mtls-dialect=desc`
  Use TLS descriptors as the thread-local storage mechanism for dynamic accesses of TLS variables. This is the default.
`-mtls-dialect=traditional`
  Use traditional TLS as the thread-local storage mechanism for dynamic accesses of TLS variables.
`-mfix-cortex-a53-835769`
`-mno-fix-cortex-a53-835769`
  Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769. This will involve inserting a NOP instruction between memory instructions and 64-bit integer multiply-accumulate instructions.
`-mfix-cortex-a53-843419`
`-mno-fix-cortex-a53-843419`
  Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419. This erratum workaround is made at link time and this will only pass the corresponding flag to the linker.
`-march=`name
  Specify the name of the target architecture, optionally suffixed by one or more feature modifiers. This option has the form `-march=arch{+[no]feature}*`, where the only permissible value for arch is ‘`armv8-a`’. The permissible values for feature are documented in the sub-section below.

  Where conflicting feature modifiers are specified, the right-most feature is used.

  GCC uses this name to determine what kind of instructions it can emit when generating assembly code.

  Where `-march` is specified without either of `-mtune` or `-mcpu` also being specified, the code will be tuned to perform well across a range of target processors implementing the target architecture.

`-mtune=`name
  Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: ‘`generic`’, ‘`cortex-a53`’, ‘`cortex-a57`’.

  Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system. The only permissible value is ‘`cortex-a57.cortex-a53`’.

  Where none of `-mtune=`, `-mcpu=` or `-march=` are specified, the code will be tuned to perform well across a range of target processors.

  This option cannot be suffixed by feature modifiers.

`-mcpu=`name
  Specify the name of the target processor, optionally suffixed by one or more feature modifiers. This option has the form `-mcpu=cpu{+[no]feature}*`, where the permissible values for cpu are the same as those available for `-mtune`.

  The permissible values for feature are documented in the sub-section below.

  Where conflicting feature modifiers are specified, the right-most feature is used.

  GCC uses this name to determine what kind of instructions it can emit when generating assembly code (as if by `-march`) and to determine the target processor for which to tune for performance (as if by `-mtune`). Where this option is used in conjunction with `-march` or `-mtune`, those options take precedence over the appropriate part of this option.

##### 3.17.1.1 `-march` and `-mcpu` feature modifiers

Feature modifiers used with `-march` and `-mcpu` can be one the following:

‘`crc`’
  Enable CRC extension.
‘`crypto`’
  Enable Crypto extension. This implies Advanced SIMD is enabled.
‘`fp`’
  Enable floating-point instructions.
‘`simd`’
  Enable Advanced SIMD instructions. This implies floating-point instructions are enabled. This is the default for all current possible values for options `-march` and `-mcpu=`.