Next: Alpha, Previous: AArch64, Up: Architectures

#### 21.4.2 x86 Architecture-specific Issues

`set struct-convention` mode
  Set the convention used by the inferior to return `struct`s and `union`s from functions to mode. Possible values of mode are `"pcc"`, `"reg"`, and `"default"` (the default). `"default"` or `"pcc"` means that `struct`s are returned on the stack, while `"reg"` means that a `struct` or a `union` whose size is 1, 2, 4, or 8 bytes will be returned in a register.
`show struct-convention`
  Show the current setting of the convention to return `struct`s from functions.

##### 21.4.2.1 Intel(R) Memory Protection Extensions (MPX).

Memory Protection Extension (MPX) adds the bound registers ‘`BND0`’ 1 through ‘`BND3`’. Bound registers store a pair of 64-bit values which are the lower bound and upper bound. Bounds are effective addresses or memory locations. The upper bounds are architecturally represented in 1's complement form. A bound having lower bound = 0, and upper bound = 0 (1's complement of all bits set) will allow access to the entire address space.

‘`BND0`’ through ‘`BND3`’ are represented in gdb as ‘`bnd0raw`’ through ‘`bnd3raw`’. Pseudo registers ‘`bnd0`’ through ‘`bnd3`’ display the upper bound performing the complement of one operation on the upper bound value, i.e. when upper bound in ‘`bnd0raw`’ is 0 in the gdb ‘`bnd0`’ it will be `0xfff...`. In this sense it can also be noted that the upper bounds are inclusive.

As an example, assume that the register BND0 holds bounds for a pointer having access allowed for the range between 0x32 and 0x71. The values present on bnd0raw and bnd registers are presented as follows:

         	bnd0raw = {0x32, 0xffffffff8e}
         	bnd0 = {lbound = 0x32, ubound = 0x71} : size 64

This way the raw value can be accessed via bnd0raw...bnd3raw. Any change on bnd0...bnd3 or bnd0raw...bnd3raw is reflect on its counterpart. When the bnd0...bnd3 registers are displayed via Python, the display includes the memory size, in bits, accessible to the pointer.

#### Footnotes

[1] The register named with capital letters represent the architecture registers.