
* Generic Exynos Memory Bus device

The Samsung Exynos SoCs have many memory buses for data transfer between DRAM
memory and MMC/sub-IP in SoC. Almost Exynos SoCs have the common architecture
for memory buses. Generally, Exynos SoC express the memory bus by using memory
bus group and block. The memory bus group has one more memory bus blocks and
OPP table (including frequency and voltage for DVFS), regulator, devfreq-event
devices. Each memory bus block has a clock for own memory bus speen and
frequency table for DVFS. There are a little different among Exynos SoCs
because each Exynos SoC has the different sub-IP and differnt memory bus.
So, this difference should be specified in devicetree file.

Required properties for memory bus group:
- compatible: Should be "samsung,exynos-memory-bus".
- operating-points: the OPP table including frequency/voltage information to
                  support DVFS (Dynamic Voltage/Frequency Scaling) feature.
- devfreq-events: the devfreq-event device to monitor the curret state of
                  memory bus group.
- vdd-mem-supply: the regulator to provide memory bus group with the voltage.

Optional properties for memory bus group:
- exynos,saturation-ratio: the percentage value which is used to calibrate
                   the memory performance count againt memory cycle count.

Required properties for memory bus block:
- clock-names : the name of clock used by the memory bus, "memory-bus".
- clocks : phandles for clock specified in "clock-names" property.
- #clock-cells: should be 1.
- frequency: the frequency table to support DVFS feature.

Example1:
	Show the hierarchy of Exynos3250 Memory Bus group. Exynos3250 divides
	the memory bus group according to power rail (regulator). Each memory
	bus group contains only one power rial and one more memory bus blocks.
	- MIF (Memory Interface) Memory bus group uses the VDD_MIF regulator
	  and has only one DMC (Dynamic Memory Controller) memory bus block
	  as following:
				|
	power rail(VDD_MIF)---->|-> memory bus for DMC blk (dmc clock)
				|

	- INT (Internal) memory Memory bus group uses the VDD_INT regulator and
	  has eight memory bus blocks as following:
				|
				|-> memory bus for PERI blk (aclk_100)
				|-> memory bus for DISPLAY blk (aclk_160)
				|-> memory bus for ISP blk (aclk_200)
				|-> memory bus for GPS blk (aclk_266)
	power rail(VDD_INT)---->|
				|-> memory bus for MCUISP blk (aclk_400_mcuisp)
				|-> memory bus for Leftbus blk (div_gdl)
				|-> memory bus for Rightbus blk (div_gdr)
				|-> memory bus for MFC blk (sclk_mfc)
				|

	Make the table for two memory bus groups which include pair information
	of between 'Rate/Voltage' and the clock of each memory bus block.
	The 'Rate' is used in devfreq ondemand governor to decide the proper
	frequency of memory bus group and then exynos-bus.c driver change the
	clock rate of each memory bus block according to freq/voltage table.

	- MIF memory bus group's frequency/voltage table
	------------------------------
	|Lv|Rate   |div_dmc |Voltage |
	------------------------------
	|L5|400000 |100000  |875000  |
	|L4|200000 |200000  |800000  |
	|L3|133000 |133000  |800000  |
	|L2|100000 |100000  |800000  |
	|L1|50000  |80000   |800000  |
	------------------------------

	- INT memory bus group's frequency/voltage table
	--------------------------------------------------------------------
	|         |PERI  |Display|ISP   |GPS   |MCUISP|GDL   |GDR   |MFC   |
	--------------------------------------------------------------------
	|         |aclk  |aclk   |aclk  |aclk  |aclk  |div   |div_  |sclk  |
	|Lv|Rate  |  _100|  _160 |  _200|  _266|  _400|  _gdl|  _gdr|  _mfc|
	--------------------------------------------------------------------
	|L6|400000|100000|200000 |200000|300000|300000|200000|200000|200000|
	|L5|200000|100000|160000 |200000|200000|200000|200000|200000|200000|
	|L4|133000|100000|100000 |100000|133000|133000|133000|133000|200000|
	|L3|100000|100000|80000  |80000 |100000|100000|100000|100000|133000|
	|L2|80000 |50000 |80000  |50000 |50000 |50000 |100000|100000|100000|
	|L1|50000 |50000 |50000  |50000 |50000 |50000 |100000|100000|80000 |
	--------------------------------------------------------------------
	|Lv|Freq  |Voltage|
	-------------------
	|L6|400000|950000 |
	|L5|200000|950000 |
	|L4|133000|925000 |
	|L3|100000|850000 |
	|L2|80000 |850000 |
	|L1|50000 |850000 |
	------------------

Example2 :
	Memory bus group/block in exynos3250.dtsi are listed below.
	Exynos3250 has two memory bus group (MIF, INT group). MIF (Memory
	Interface) memory bus group includes one memory bus block between
	DRAM and eMMC. Also, INT (Internal) memory bus group includes eight
	memory bus blocks which support each sub-IP between DRAM and sub-IP.

	memory_bus_mif: memory_bus@0 {
		compatible = "samsung,exynos-memory-bus";

		operating-points = <
			400000 875000
			200000 800000
			133000 800000
			100000 800000
			50000  800000>;
		status = "disabled";

		blocks {
			dmc_block: memory_bus_block1 {
				clocks = <&cmu_dmc CLK_DIV_DMC>;
				clock-names = "memory-bus";
				frequency = <
					400000
					200000
					133000
					100000
					50000>;
			};
		};
	};

	memory_bus_int: memory_bus@1 {
		compatible = "samsung,exynos-memory-bus";

		operating-points = <
			400000 950000
			200000 950000
			133000 925000
			100000 850000
			80000  850000
			50000  850000>;

		status = "disabled";

		blocks {
			peri_block: memory_bus_block1 {
				clocks = <&cmu CLK_DIV_ACLK_100>;
				clock-names = "memory-bus";
				frequency = <
					100000
					100000
					100000
					100000
					50000
					50000>;
			};

			display_block: memory_bus_block2 {
				clocks = <&cmu CLK_DIV_ACLK_160>;
				clock-names = "memory-bus";
				frequency = <
					200000
					160000
					100000
					80000
					80000
					50000>;
			};

			isp_block: memory_bus_block3 {
				clocks = <&cmu CLK_DIV_ACLK_200>;
				clock-names = "memory-bus";
				frequency = <
					200000
					200000
					100000
					80000
					50000
					50000>;
			};

			gps_block: memory_bus_block4 {
				clocks = <&cmu CLK_DIV_ACLK_266>;
				clock-names = "memory-bus";
				frequency = <
					300000
					200000
					133000
					100000
					50000
					50000>;
			};

			mcuisp_block: memory_bus_block5 {
				clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
				clock-names = "memory-bus";
				frequency = <
					400000
					200000
					50000
					50000
					50000
					50000>;
			};

			leftbus_block: memory_bus_block6 {
				clocks = <&cmu CLK_DIV_GDL>;
				clock-names = "memory-bus";
				frequency = <
					200000
					200000
					133000
					100000
					100000
					100000>;
			};

			rightbus_block: memory_bus_block7 {
				clocks = <&cmu CLK_DIV_GDR>;
				clock-names = "memory-bus";
				frequency = <
					200000
					200000
					133000
					100000
					100000
					100000>;
			};

			mfc_block: memory_bus_block8 {
				clocks = <&cmu CLK_SCLK_MFC>;
				clock-names = "memory-bus";
				frequency = <
					200000
					200000
					200000
					133000
					100000
					80000>;
			};
		};
	};

Example3 :
	Usage case to handle the frequency/voltage of memory bus on runtime
	in exynos3250-rinato.dts are listed below.

	&memory_bus_mif {
		devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
		vdd-mem-supply = <&buck1_reg>;
		status = "okay";
	};

	&memory_bus_int {
		devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
		vdd-mem-supply = <&buck3_reg>;
		status = "okay";
	};
